Aerospace and Electronic Systems Magazine March 2017 - 6
Refining Fault Trees Using Aviation Definitions for Consequence Severity
ure event map into a high-level risk associated with a particular
consequence.
Fault trees are commonly used in system verification, validation, and certification (VV&C). However, fault trees are also useful
in the design process, allowing engineers to identify areas where
mitigations might be introduced to reduce overall system risk [8].
The key to quantifying risks is the introduction of logic gates
(AND and OR gates) that can be used to combine failure probabilities. When either of a pair of events might result in the same consequence, an OR gate is used to combine their individual event probabilities. When a consequence only occurs as the result of multiple
events occurring together, an AND gate is used to combine their
probabilities. Design mitigations are typically incorporated into a
fault tree using an AND gate, as shown in Figure 1.
The function of each logic gate is to map two events to a single outcome. The input events and the output events can both be
thought of as probability distributions over a discrete set of system
states. In a conventional fault tree analysis, these states have two
possible values: {fault-free, faulted}. The associated distribution
assigns a value of probability to each state, such that probabilities
sum to one. The gate combines two such distributions to compute
an output probability distribution.
In order to embed aviation severity levels into a fault tree, it becomes necessary to embrace the notion that the system states may
take on more than two possible values. In the case of aviation severity analysis, states can take one of five possible discrete values
from the following set: {no hazard, minor, major, hazardous, and
catastrophic}. The corresponding distribution of state probabilities
assigns a positive value to each of these five categories, with values summing to one.
Here we introduce a notation that allows us to model how gates
map input probability distributions to output probability distributions. This notation allows us to represent binary and multilevel
analyses in a common manner. To this end, label the input states
A and B, and label the output state C. The probability distributions associated with each set of discrete states are labeled P(A),
P(B), and P(C). The purpose of the gate is to operate on the two
input distributions to obtain an output distribution. Let the label f
describe the mathematical operation performed by the gate on the
two input distributions.
P C f P A , P B
C
C
A, B | g A, B
The probability for each possible output state value is the sum of
the probability of each pair in this set. Summing over all the pairs
gives the output probability:
P C
P A, B .
(4)
P A
, B P A P B .
(5)
Combining (4) and (5) we obtain the following equation that models outcome probabilities when input probabilities are independent.
P C
P A P B
(6)
(A,B) C
Both AND and OR gates can be analyzed with (6). The primary
difference between the AND and OR gates is in the definition of
the mapping function g, as described by (2).
CHALLENGES MODELING AVIATION SEVERITY WITH BINARY
LOGIC
For the binary logic case, all state variables take one of two discrete
values: A,B,C ∈ {0,1}. The output probability can be computed using (6) for both the AND and OR gates. The primary difference
between these gates is in the definition of the mapping function
g, as described by (2). For the OR gate, the g function is a logical
OR, which operates on inputs A and B according to the logic table
shown as Table 2. For the AND gate, the g function is a logical
AND, as described by Table 3.
It is common in binary analysis to track only the faulted probability (and not the probability distribution) at the output of each
(1)
(2)
In general, for a state with N possible values, there are N2 permutations of inputs (A and B) but only N possible outputs. This
means that there may be many input pairs that map to any given
output state. For analysis it is useful to identify the set of all possible input pairs (A,B) that result in a particular outcome C and
label that set ΩC.
6
A,BC
In this article, we assume that the two input events are always
independent, such that the joint probability distribution P(A,B) can
be defined through multiplication.
What makes each gate different is how output state values are defined from input state values. To describe this process, define a
mapping g that relates any pair of discrete input values to a particular discrete output value.
C g A, B
(3)
IEEE A&E SYSTEMS MAGAZINE
Table 2.
Conventional (Binary) OR Table
Binary OR
A=0
A=1
B=0
Ω0
Ω1
B=1
Ω1
Ω1
Table 3.
Conventional (Binary) AND Table
Binary AND
A=0
A=1
B=0
Ω0
Ω0
B=1
Ω0
Ω1
MARCH 2017
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