Aerospace and Electronic Systems Magazine June 2017 - 13

Baldi et al.

Figure 9.

High-level view of the breadboard architecture.

for the LDPC(512, 256) code. Neglecting the impact of possible
inaccurate frame synchronization, we can compute the frame error
rate (FER) as FER = 1 - (1 - CER)M that, for sufficiently small
CER, can be approximated as FER ≈ M · CER. The target value is
FER = 10−3. It is possible to verify that the values of Es/N0 required
to satisfy the requirement on the CER value, reported in Table 5,
permit also to satisfy the requirement on the FER value for any
number of codewords.
Finally, as mentioned, the UCER performance of the new
codes is at least as important as the CER performance. Therefore,
it deserves to be discussed as well. From the UCER viewpoint,
there is a fundamental difference between the adoption of iterative
decoding algorithms, like SPA-LLR, MS, and NMS, and the adoption of the MRB algorithm.
Iterative algorithms implement incomplete decoders, which
means they are able, in most cases, to detect a decoding failure.
This is also the feature which permits us to apply the hybrid approach. The residual fraction of errors, that is the case when failures
are not detected, is responsible for the UCER, which is normally
much smaller than the CER. The UCER curve of the LDPC(128,
64) code, decoded by using the SPA-LLR algorithm, is shown in
Figure 8. The curve has been obtained under the assumption of no
quantization. We see that at Es/N0 ≈ 2 dB, that is, according to Table
5, the value required to achieve CER = 10−5, is able to guarantee
also UCER ≤ 10−9.
The situation is different for the MRB algorithm (and, consequently, for the hybrid algorithm). The latter, in fact, implements
a complete decoder, which means that the decoder has no error
detection capability and UCER = CER. So, looking, for example,
at Figure 7a, we should conclude that values of Es/N0 much larger
than that necessary for satisfying the requirement on the CER must
be applied, this way frustrating the advantage of using the MRB
algorithm. In this case, however, it is possible to exploit the CRC.
The latter is deputed to detect errors at the output of the MRB
decoder and, taking into account the properties of the error patterns, that are LDPC codewords in turn, it is possible to verify
[26] that its performance is quite adequate to comply with the
UCER requirement. The resulting curve for the LDPC(128, 64)
JUNE 2017

code is shown in Figure 8. The analysis could be repeated for the
LDPC(512, 256) code, for which satisfying the requirement on the
UCER is even simpler.

HW IMPLEMENTATION CONSIDERATIONS
The study activity includes an HW proof-of-concept of the new
advanced uplink coding techniques. For this purpose, a breadboard
able to demodulate and decode uplink signals has been developed.
For the breadboard design, the current telemetry, tracking, and
command (TT&C) architecture and the optimizations required to
incorporate the novel techniques must be considered; at the same
time, the demonstrator goals, algorithm validation, and evaluation
drive the overall design.
The architecture is based on a System-on-Chip (SoC) approach fully contained in an FPGA device, where a microprocessor is embedded, performing digital signal processing (DSP)
functions for TT&C transponder processing. The microprocessor interfaces all DSP blocks and all other peripherals on-chip
through a bus, which allows it to control and configure every
TC receiver processing unit. This approach offers the advantage
of a configurable, modular, and synchronous architecture, allowing portability, modification, or addition of DSP cores. The
breadboard architecture is presented in Figure 9, where the HW/
Software (SW) partition of the different TC processing units is
also shown.
This flexible platform permits us to deal with both NE and DS
links requirements. The modular architecture allows incorporating
critical components for test-bench fulfillment, such as monitoring
units or communication interfaces for configuration and control
in the test campaign. Furthermore, for the low data-rate DS scenario, most of the novel functions can be fully implemented in the
SW domain. In particular, SW processing is well-suited for closing
complex carrier and subcarrier tracking loops with HW domain.
In addition, SW flexibility can support the higher complexity of
MRB decoding, where a mixed HW/SW implementation is foreseen. Indeed, the SW part of the MRB algorithm can be in charge
of matrix operation and vector reordering, while the HW paral-

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