Aerospace and Electronic Systems Magazine July 2017 Tutorial XI - 28

Tutorial:

DOI. No. 10.1109/MAES.2017.150260

Are PLLs Dead? A Tutorial on Kalman Filter-Based
Techniques for Digital Carrier Synchronization
Jordi Vilà-Valls, Centre Tecnològic de Telecomunicacions de Catalunya (CTTC/CERCA),
Barcelona, Spain
Pau Closas, Northeastern University, Boston, MA, USA
Monica Navarro, Carles Fernández-Prades, Centre Tecnològic de Telecomunicacions de
Catalunya (CTTC/CERCA), Barcelona, Spain

Carrier synchronization is a fundamental stage in the receiver
side of any communication or positioning system. Traditional
carrier phase tracking techniques are based on well-known
phase-locked loop (PLL) closed-loop architectures, which are
still the methods of choice in modern receivers. Those techniques are well understood, easy to tune, and perform well
under benign propagation conditions, but their applicability is seriously compromised in harsh propagation environments, where the signal may be affected by high dynamics,
shadowing, strong fadings, multipath effects, or ionospheric
scintillation. From an optimal filtering standpoint, the Kalman filter (KF) is clearly a powerful alternative, but the synchronization community seems still reluctant to exploit all the
potential it has to offer. The purpose of this article is twofold:
i) to review the basics and state of the art on both PLL and
KF-based tracking techniques and ii) to present and justify
the reasoning behind the systematic use of KF-based tracking
approaches instead of the well-established PLL-based architectures from both theoretical and practical points of view. To
support the discussion, two specific scenarios of interest to the
aerospace community are numerically evaluated: robust carrier tracking of global navigation satellite systems' signals and
synchronization in a deep space communications system.

Authors' current addresses: J. Vilà-Valls, M. Navarro, C.
Fernández-Prades, CTTC, Statistical Inference for Communications and Positioning, Centre Tecnològic de Telecomunicacions de Catalunya, Carl Friedrich Gauss, 7 Castelldefels, Barcelona 08860 Spain, E-mail: ({jordi.vila,monica.navarro,carles.
fernandez@cttc.cat); P. Closas, Department of Electrical and
Computer Engineering, Northeastern University, Boston, MA
02115, USA. E-mail: closas@northeastern.edu
This work was supported by the Spanish Ministry of Economy
and Competitiveness through project TEC2015-69868-C2-2-R
(ADVENTURE) and by the Government of Catalonia under
grant 2014-SGR-1567.
Manuscript received November 25, 2015, revised November
30, 2016, and ready for publication January 31, 2017.
Review handled by W. D. Blair.
0885/8985/17/$26.00 © 2017 IEEE
28

INTRODUCTION
The main goal of this article is to provide a tutorial-style discussion on why traditional synchronization loop architectures, inherited
from the analog era, may be abandoned in modern digital receivers
and to move forward toward the design and actual use of more flexible, robust and powerful Kalman filter (KF)-based synchronization
schemes. Carrier synchronization is a key process in most electronic
devices involved in aerospace systems, and it is typically carried out
following a two-stage approach: acquisition and tracking. The first
stage detects the presence of the desired signal and provides a coarse
estimate of its synchronization parameters, and the second one refines those estimates, filtering out noise and tracking any possible
time variation [1]. In the present work, we are concerned with the
analysis of the carrier phase (CP) tracking problem. Hence, acquisition and time delay synchronization are not discussed.
Digital CP tracking techniques implemented in conventional receivers rely on well-known phase-locked loop (PLL) architectures [2],
[3], [4] that set an output signal's phase relative to an input reference
signal's phase. Those circuits are widely used in positioning systems,
communications, computers, control, and measurement applications
for frequency synthesis, clock and data recovery, clock distribution,
and other more specialized functions. The signals of interest may be
any periodic waveform but are typically sinusoids or digital clocks.
Digital PLLs can be implemented in hardware (usually with mixed
signal or all-digital integrated circuits in complementary metal oxide
semiconductor technology [5], [6], [7] and targeting frequencies on the
order of gigahertz and above [8]), but the rapid evolution of programmable devices, such as field-programmable gate arrays, digital signal
processors, microcontrollers, and general-purpose processors, enables
software-defined implementations targeting frequencies up to hundreds
of megahertz, in which the designer trades electronic components for
computation resources [9], [10]. This approach provides advantages,
such as easy customization of the feedback loop and a drastic reduction
in the development cost, when compared with the hardware counterpart. However, the underlying design principles remain the same regardless of the technology of choice for the implementation.
The performance obtained with those techniques is generally
good enough in benign propagation conditions, but they have been
shown to deliver poor estimates or even fail under harsh propa-

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