Aerospace and Electronic Systems Magazine August 2017 - 49
Leclère, Botteron, and Farine
Table 1.
Summary of the Memory Requirement and Processing Time for the Different Implementations
Secondary Code
Removal
Pre-FFT
Post-FFT
Memory for Storage and
Combinations (bit)
Implementation
Processing Time (Clock Cycle)
Theoretical direct correlation
(Figures 2 & 14)
-
N(K + 2) + 2LN or N(2K + 4) +
NZ,D(K + 2) + 2LN
Sequential (Figures 3 & 15)
4NP(B0 + ⌈log2 NS⌉)
NP(2K NS2 + 3) + 2NZ + 2L
Parallel (Figures 4 & 16)
4NPNS(B0 + ⌈log2 NS⌉)
NP[4K(NS - 1) + 5] + NZ[K(NS -
1) + 2] + 2L
Sequential (Figures 6 & 19)
2NP(B1 + ⌈log2 NS⌉)
NP(2K NS2 + 3) + NZ (K NS2 + 1)
+ 2L
Parallel (Figures 7 & 20)
2NPNS(B1 + ⌈log2 NS⌉)
NP(2KNS + 3) + NZ(KNS + 1) +
2L
Memory + Sequential
(Figures 5 & 18)
2NP[(NS + 1)B1 + ⌈log2 NS⌉]
NP[K(NS2 - 1) + NS + 4] +
NZ[K(NS - 1) + 2] + 2L
Memory + Sequential SCCC*
(Figures 8 & 21)
2NPNSB1
NP[K(NS2 + 2NS - 2) + 4] +
NZ[K(NS - 1) + 2] + 2L
Memory + Parallel SCCC
(Figures 9 & 22)
2NPNSB1
NP[K(3NS - 2) + 4] + NZ[K(NS -
1) + 2] + 2L
Memory + FFT SCCC (Figures
10 & 23)
2NPNSB1
NP[K(4NS + NZ,S - 2) + 4] +
NZ[K(NS - 1) + 2] + 2L + 2LS
+ NS
* SCCC stands for secondary code circular correlation.
practical for hardware implementations. The processing time and
memory usage of all the implementations are given in Table 1.
first row is the primary code pT padded with NP zeros, and the
xi are built from two consecutive periods of the incoming code,
T
CORRELATION OVER THE PRIMARY CODE PERIOD AND
COMBINATIONS
Instead of computing the circular correlation over one entire period of the secondary code, it is possible to perform a circular
correlation over one period of the primary code, repeat this for
multiple consecutive periods, and then combine the results according to the chips of the secondary code, as proposed in [12].
Therefore, the output y can be computed by portions equivalent
to the period of the primary code. For example, considering that
the secondary code has four chips (example that we will use
along this article for the illustrations), the four portions of the
output can be obtained as
y 0 s0 PT x 0 + s1PT x1 + s2 PT x 2 + s3PT x3
y
s P x +s P x +sP x +s P x
y = 1 = 3 T 0 0 T 1 1 T 2 2 T 3,
y 2 s2 PT x 0 + s3PT x1 + s0 PT x 2 + s1PT x3
y 3 s1PT x0 + s2 PT x1 + s3PT x 2 + s0 PT x3
(7)
where the yi are the different portions of the output containing
NP samples, PT is a Toeplitz matrix of size NP × 2NP where the
AUGUST 2017
i.e., xi = xi× N P xi × N P +1 xi × N P + 2 N P −1 , they contain thus 2NP
samples (see [13], chapter 6 for more details about how to obtain
this equation). Note that (7) is not an approximation of (5), the output y is exactly the same in both cases. Only the way to compute
y is different.
The Toeplitz matrix PT can be embedded into a circulant matrix
of size 2NP × 2NP by adding NP rows [25], therefore the product between PT and a vector of 2NP points can be computed as a circular
correlation using three FFTs of length 2NP, where the second half
of the output is discarded. If the length of the FFTs has a constraint
(such as to be a power of two), zeros can be added to the local
and incoming sequences to achieve the desired length. Since we
focus on FPGA implementations, we consider this constraint, and
thus for the acquisition of the L5, E5a, and E5b signals, the length
of the FFT will be NFFT = 2NP + NZ = 65,536 (since the minimum
for 2NP is 40,920). This value for the FFT length can be used for
sampling frequencies up to 32.768 MHz. Note that there are methods to optimize this double length circular correlation for FPGA
implementations [31], [32] but we do not consider them in the following discussions since this circular correlation is present in all
the implementations discussed.
Coming back to (7), the multiplication by the secondary code
chips can be done at different stages. If the different combinations
according to the secondary code delay are performed before the
FFT-based correlation, (7) becomes
IEEE A&E SYSTEMS MAGAZINE
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