Aerospace and Electronic Systems Magazine August 2017 - 50
Acquisition of GNSS Signals with Secondary Code
y 0
PT
y1 = 0
y 2
0
y
0
3
PT
0
=
0
0
0
PT
0
0
0
PT
0
0
0
PT
0
0
0
0
PT
0
0 s0
0 s3
0 s2
PT s1
0 a 0
0 a1
0 a 2
PT a3
s1
s0
s3
s2
s2
s1
s0
s3
s3 x 0
s2 x1
s1 x 2
s0 x3
(8)
Implementation of the pre-FFT secondary code removal (see (8))
computing each combination of the input sequentially. See the timing
diagram in Figure 15.
PT a 0
Pa
= T 1,
PT a 2
PT a3
IMPLEMENTATION OF THE PRE-FFT SECONDARY CODE
REMOVAL IN A SEQUENTIAL WAY
S
where a j = i = 0 s((i − j )) xi, the double parenthesis meaning a modulo-NS operation. Since the secondary code is removed before the
FFTs, we will talk about pre-FFT secondary code removal. If the
different combinations are performed after the FFT-based correlation, (7) becomes
N −1
y 0 s0
y1 = s3
y 2 s2
y 3 s1
s1
s0
s3
s2
s2
s1
s0
s3
s3 PT x 0
s2 PT x1
s1 PT x 2
s0 PT x3
s0
s
= 3
s2
s1
s1
s0
s3
s2
s2
s1
s0
s3
s3 r0
s2 r1
,
s1 r2
s0 r3
(9)
where ri = PT xi. Since the secondary code is removed after the
FFTs, we will talk about post-FFT secondary code removal. The
notation ai and ri are used to facilitate the link between the equations and the figures. Note that ri has a clear meaning, since we can
write (assuming the Doppler is correctly removed)
ri = si −Δ rp + ηi ,
(10)
where Δ is the unknown delay of the incoming secondary code, rp
is the autocorrelation of the primary code, and ηi is the noise.
In both (8) and (9), there are NS FFT-based correlations over
at least 2NP points. For the combinations, (8) uses vectors of 2NP
points, whereas (9) uses vectors of NP points. Thus, (9) requires
slightly less operations than (8). One can check that these two
equations require more operations than the direct correlation of (5).
In the next subsections, we will study the FPGA implementation of both equations, testing the secondary code delays sequentially or in parallel, and using or not memory to save temporary
results. For the evaluation of the processing time, we will consider
a streaming data flow, i.e., an FFT that can process the data in a
continuous way.
50
Figure 3.
In (8), there are NS correlations between the local primary code p
and the combinations of the different periods of the incoming signal (a0, a1, ...). The corresponding implementation computing each
combination sequentially is shown in Figure 3. The accumulator
used before the FFT is implemented with an adder and a memory
having 2NP addresses, to accumulate over NS samples (one sample
of each period), as shown in Figures 12 and 13. The processing
starts by accessing all the portions of the input (x0, x1, ...), and
when the last one is accessed, the first combination a0 is available
and its correlation with the local code p is computed to obtain y0.
Then, x0, x1, ... can be accessed again immediately to compute the
second combination, and so on and so forth, until the NS combinations have been tested. The processing time is approximately 2NS
times higher than the one of the direct correlation implementation.
With this implementation, the memory needed is twice 2NP(B0
+ ⌈log2 NS⌉) bits for the accumulation because the signal is complex, where B0 denotes the number of bits used to quantize xi.
IMPLEMENTATION OF THE PRE-FFT SECONDARY CODE
REMOVAL IN A PARALLEL WAY
It is also possible to compute the different combinations (a0, a1,
...) in parallel using NS accumulators, as shown in Figure 4. In this
case, the processing also starts by accessing x0, x1, ..., and when
the last one is accessed, a0, a1, ... are available in the accumulators'
memory. Then, each ai is read successively and the correlation with
the local code p is computed to obtain yi. Then, for the next data
stream, the portions of the input can be accessed again only when
the last combination is read, which implies that the processing time
is divided by a factor lower than NS compared to the previous sequential implementation.
With this implementation, the memory requirements are higher
since 2NPNS (B0 + ⌈log2 NS⌉) bits need to be stored for the accumulation.
These two pre-FFT implementations are the extreme cases,
where either only one combination is computed at a time, or all
the combinations are computed simultaneously. However, it is also
possible to test only several combinations, using one accumulator
per combination. For example, the timing diagram considering two
accumulators is given in Figure 17.
IEEE A&E SYSTEMS MAGAZINE
AUGUST 2017
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