Aerospace and Electronic Systems Magazine August 2017 - 53

Leclère, Botteron, and Farine
Table 2.

Parameters Selected for a "Low-Cost" and a "HighEnd" Receiver
Parameters

Low-Cost

High-End

B0

4

12

fS

20.48 MHz

32.768 MHz

NP

20,480

32,768

NFFT

65,536

65,536

NZ = NFFT - 2NP

24,576

0

L

0

0

NS

20

20

NFFT,S

64

64

NZ,S = NFFT,S -
2NS

24

24

B1

16

16

K

100

100

LS

0

0

N

409,600

655,360

NZ,D

229,376

786,432

0

0

LN

these FFTs need sequences that have a length that is a power of
two. None of the secondary code currently available has such a
length (except on the data channel of the E5b signal). Therefore,
zero-padding must be used, and the length of the sequences must
at least double (to keep the periodicity and avoid losses). For example, with the GPS L5 pilot secondary code that has 20 bits, the
FFTs length will be 64 bits.
The process is similar to the previous implementation, except
that more samples are needed to compute the circular correlation,
and therefore the processing time is longer. Moreover, the resources required by an FFT of 64 points in terms of logic, memory, and
multipliers are not negligible, therefore such FFT will likely require more resources than the implementation of NS accumulators
(except maybe if NS = 100, as with the E5a and E5b signals). Consequently, the use of the FFT for the circular correlation over the
secondary code is not recommended.

SUMMARY
Table 1 provides a summary of the memory needed and of the processing time for each considered implementation. Let's first have
a look on the sequential implementations. Comparing the pre-FFT
and post-FFT sequential implementations (Figures 3 and 6), the
second one requires a higher processing time due to the zero-padding (this extra time can be significant if NZ is large), and its required memory is multiplied by (B1 + ⌈log2NS⌉)/2(B0 + ⌈log2NS⌉).
Usually, B0 is rather small (since the incoming signal is typically
quantized with 2 bits and the local carrier replica as well [33]),
AUGUST 2017

and B1 is not small because the FFT requires a certain number of
bits to provide accurate results (typically 16 bits, from experience).
Thus, the memory requirements for both implementations can be
relatively close. Therefore, the pre-FFT sequential implementation
seems more interesting than the post-FFT sequential implementation.
For the post-FFT sequential implementation using a memory
(Figure 5), its processing time is roughly half the one of the postFFT sequential implementation (Figure 6), whereas the memory
is multiplied by a factor close to NS. Note however that the FFTs
require a significant amount of memory, and that the incoming
signal is also stored (see Figure 1), therefore the total amount of
memory needed for the acquisition is multiplied by a factor less
than NS. For the post-FFT implementation using a memory with
a sequential secondary code circular correlation (Figure 8), there
is a slight increase in the processing time and a slight decrease in
the memory requirements. Thus, the most suitable of these three
post-FFT sequential implementations will depend on the context
and design constraints.
Let's now compare the parallel implementations. Comparing
the pre-FFT and post-FFT parallel implementations (Figures 4 and
7), the second one has a lower processing time (by a factor at most
two), whereas the memory is multiplied again by a factor (B1 +
⌈log2NS⌉)/2(B0 + ⌈log2NS⌉). Therefore, there is probably an advantage for the post-FFT implementation, but the context and the
design should be taken into account to make a precise evaluation.
For the post-FFT implementation using a memory with a parallel secondary code circular correlation (Figure 9), its processing
time is higher than the one of the post-FFT parallel implementation (Figure 7) by a factor less than 3/2, whereas its memory is
multiplied by a factor B1/(B1 + ⌈log2NS⌉), which is smaller than
one. Therefore, it is again difficult to decide between these two
implementations without more information about the context and
the design.
For the post-FFT implementation using a memory with an FFTbased secondary code circular correlation (Figure 10), the processing time is longer than the one of the post-FFT implementation
using a memory with a parallel secondary code circular correlation
(Figure 9) by a factor of at least 4/3, and the memory requirement
is slightly higher due to the small FFTs. Therefore, this implementation is less efficient and not interesting.
To have a more concrete evaluation, let's consider two examples, one corresponding to a "low-cost" receiver where the incoming signal is quantized with few bits and sampled with a low
frequency, and one corresponding to a "high-end" receiver using
more bits for the quantization and a higher sampling frequency.
The parameters selected considering the GPS L5 pilot signal are
shown in Table 2, and the results are shown in Tables 3 and 4.
For the evaluation of the memory required by the FFTs, we
have considered the FFT core provided by Altera, and such FFT
of 65,536 points using a streaming data flow and 16 bits of resolution implemented on an Altera Stratix V FPGA requires about
12.5 Mbits of memory [32]. The memory required by an Altera
FFT roughly doubles when the length is doubled [34]; therefore,
we can assume that if it would exist, an FFT of 1,048,576 points
would require approximately 200 Mbits. Note that nonetheless,

IEEE A&E SYSTEMS MAGAZINE

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