Aerospace and Electronic Systems Magazine August 2017 - 54

Acquisition of GNSS Signals with Secondary Code
Table 3.

Numerical Application with the L5 Pilot Signal for a "Low-Cost" Receiver
Secondary
Code
Removal

Pre-FFT
Post-FFT

Memory
for FFTs*
(Mbit)

Memory for Storage and Combinations (bit)

Processing Time (Clock Cycle)

Theoretical direct
correlation (Figures 2 & 14)

200

-

4,080NP + 102NZ,D = 106,954,752

Sequential (Figures 3 & 15)

37.5

36NP = 737,280

80,003NP + 2NZ = 1,638,510,592

Parallel (Figures 4 & 16)

37.5

720NP = 14,745,600

7,605NP + 1,902NZ = 202,493,952

Sequential (Figures 6 & 19)

37.5

42NP = 860,160

80,003NP + 40,001NZ = 2,621,526,016

Parallel (Figures 7 & 20)

37.5

840NP = 17,203,200

4,003NP + 2,001NZ = 131,158,016

Memory + Sequential
(Figures 5 & 18)

37.5

682NP = 13,967,360

39,924NP + 1,902NZ = 864,387,072

Memory + Sequential SCCC
(Figures 8 & 21)

37.5

640NP = 13,107,200

43,804NP + 1,902NZ = 943,849,472

Memory + Parallel SCCC
(Figures 9 & 22)

37.5

640NP = 13,107,200

5,804NP + 1,902NZ = 165,609,472

Memory + FFT SCCC
(Figures 10 & 23)

37.5

640NP = 13,107,200

10,204NP + 1,902NZ = 255,721,492

Implementation

* These values are for unoptimized FFT implementations and could be reduced by about 75% [32].

Table 4.

Numerical Application with the L5 Pilot Signal for "High-End" Receiver
Secondary
Code
Removal

Pre-FFT
Post-FFT

Memory
for FFTs*
(Mbit)

Memory for Storage and Combinations (bit)

Processing Time (Clock Cycle)

Theoretical direct
correlation (Figures 2 & 14)

400

-

4,080NP + 102NZ,D = 213,909,504

Sequential (Figures 3 & 15)

37.5

68NP = 2,228,224

80,003NP + 2NZ = 2,621,538,304

Parallel (Figures 4 & 16)

37.5

1,360NP = 44,564,480

7,605NP + 1,902NZ = 249,200,640

Sequential (Figures 6 & 19)

37.5

42NP = 1,376,256

80,003NP + 40,001NZ = 2,621,538,304

Parallel (Figures 7 & 20)

37.5

840NP = 27,525,120

4,003NP + 2,001NZ = 131,170,304

Memory + Sequential
(Figures 5 & 18)

37.5

682NP = 22,347,776

39,924NP + 1,902NZ = 1,308,229,632

Memory + Sequential
SCCC* (Figures 8 & 21)

37.5

640NP = 20,971,520

43,804NP + 1,902NZ = 1,435,369,472

Memory + Parallel SCCC
(Figures 9 & 22)

37.5

640NP = 20,971,520

5,804NP + 1,902NZ = 190,185,472

Memory + FFT SCCC
(Figures 10 & 23)

37.5

640NP = 20,971,520

10,204NP + 1,902NZ = 334,364,692

Implementation

* These values are for unoptimized FFT implementations and could be reduced by about 75% [32].

these amounts of memory could be significantly reduced (by about
75%) by using an alternative implementation of the circular correlation [32], although not reported in Tables 3 and 4.
Note also that to store the incoming signal (see Figure 1), an additional memory is needed, for example of 2NPNS × B = 1,636,800
bits if B = 2 bits are used for the quantization.
54

In Tables 3 and 4, we clearly see that the pre-FFT and post-FFT
sequential implementations require much less memory than the other implementations, but they have a much longer processing time.
It can also be seen that when there is no zero-padding (high-end
receiver case), the post-FFT implementation has the same processing time as the pre-FFT one but uses less memory. Still consider-

IEEE A&E SYSTEMS MAGAZINE

AUGUST 2017



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