Aerospace and Electronic Systems Magazine August 2017 - 55
Leclère, Botteron, and Farine
ing a sequential implementation, the use of a memory to store the
correlation results increases a lot the memory for a small decrease
of the processing time. Finally, the parallel implementations use a
lot of memory but decrease a lot the processing time, and the postFFT parallel implementations are better than the pre-FFT parallel
implementation since the processing time and the memory can both
be lower. The parallel FFT implementations have a processing time
close to the one of the theoretical direct correlation, or even better,
for the high-end receiver (because the FFT for the direct correlation
uses 221 points due to the chosen sampling frequency), whereas the
direct correlation requires a much higher amount of memory for the
very large FFTs (and a higher amount of logic, not mentioned in the
tables). In conclusion, we can say that with both receivers, the most
suitable implementations are post-FFT parallel implementations.
And comparing both receivers, the high-end one uses more memory
and the processing time is longer due to the higher quantization and
sampling frequency. Of course, the sequential and parallel implementations considered here are the two extremes; it is also possible
to test only few delays for the secondary code in parallel, which
would balance the memory requirements and the processing time.
The main idea is to rewrite the local secondary code as
s = (s − 1) + 1
= s′ + 1,
where 1 is a vector composed of ones only. In this case, the elements of s′ can have as value 0 or -2. Note that the local secondary code is not modified, it is simply expressed as the sum of two
codes, and this concerns only the local code, not the incoming one.
Thus, (8) and (9) can respectively be rewritten as
y 0 PT
y1 = 0
y 2 0
y 3 0
NEW METHOD TO REDUCE THE PROCESSING TIME
In this section, we describe a method that reduces the theoretical
number of operations related to the secondary code correlation by
about 50%, and discuss its application for a hardware implementation. Note that this method is not an approximation, i.e. the output
will be exactly the same as previously, and thus the performance in
terms of sensitivity is exactly the same.
AUGUST 2017
0
PT
0
0
0
0
PT
0
s0′ + 1
′
s3 + 1
s2′ + 1
s1′ + 1
PT
0
=
0
0
USE OF DUAL READ ACCESS MEMORY
In the previous discussions, it was assumed that only one sample
could be read from a memory at each clock cycle. However, the
memories inside FPGAs usually propose a dual read access, and
thus it is possible to read simultaneously two samples stored at different addresses. This can be used to improve the processing time
of the implementations discussed previously, but not all of them
can benefit from it, as discussed next.
For Figure 3, if we can access two samples of xi,n at the same
time, the processing time can be halved since the bottleneck is in
the access of the input signal. However, since xi,n is after the mixer
with the local carrier, it would require two local carrier generators,
therefore it is not so straightforward to implement. For Figure 4,
the processing time can be reduced only a little bit, at most by a
factor 4/3 because the bottleneck is on the correlation computation,
with the same complexity as before. For Figures 5 and 8, the processing time can be almost halved since the bottleneck is mainly
related to the memory reading, and it is simple to implement since
it is related to the memory storing the correlation results and does
not complicate the access to xi,n. For Figure 9, the processing time
can be reduced only a little bit, at most by a factor 6/5 because the
bottleneck is mostly on the correlation computation, with the same
simplicity as previously. For the other implementations (Figures
6, 7, and 10), having a double read access cannot be exploited and
thus the processing time will stay the same.
(12)
0
0
0
PT
s1′ + 1 s′2 + 1
s0′ + 1 s1′ + 1
s3′ + 1 s0′ + 1
s2′ + 1 s3′ + 1
0
PT
0
0
0
0
PT
0
s3′ + 1 x 0
s2′ + 1 x1
s1′ + 1 x 2
s0′ + 1 x3
(13)
0 a′0 x Σ
0 a1′ x Σ
+
,
0 a′2 x Σ
PT a′3 x Σ
and
y 0 s0′ + 1
y1 = s3′ + 1
y 2 s2′ + 1
y 3 s1′ + 1
s0′
′
s
= 3
s2′
s1′
s1′ + 1
s0′ + 1
s3′ + 1
s′2 + 1
s1′
s0′
s3′
s′2
s2′
s1′
s0′
s3′
s2′ + 1
s1′ + 1
s0′ + 1
s3′ + 1
s3′ + 1 r0
s′2 + 1 r1
s1′ + 1 r2
s0′ + 1 r3
(14)
s3′ r0 rΣ
s2′ r1 rΣ
+
,
s1′ r2 rΣ
s0′ r3 rΣ
S
with a′j = i =S0 s((′ i − j )) xi , x Σ = i =S0 xi and rΣ = i = 0 r.i Note that
(13) and (14) are not approximations of (8) and (9), the output y
is exactly the same in all the cases. Only the way to compute y is
different. Since xΣ and rΣ are the sum of signals still containing
a secondary code, one may think that they contain mostly noise
and thus that they are not useful and could be removed from the
computation, but this would be a wrong idea. Even if they indeed
contain mostly noise, these are simply intermediate results, and the
noises present will be subtracted to the same noises when adding
xΣ and a′i or rΣ and the combinations of ri, and at the end the output y will have the same noise component as with the traditional
method. Removing xΣ or rΣ from (13) and (14) would change the
operation done, add more noise, and therefore impact the sensitivity. Therefore, (13) and (14) should be applied as it is.
In (8), the computation of one combination requires (NS -
1)2NP additions, thus the computation of the NS combinations
requires NS (NS - 1)2NP = ( N S2 - NS) 2NP additions. In (13), the
computation of xΣ requires (NS - 1) 2NP additions, and then for
each output yk, the computation of one combination a′i requires
IEEE A&E SYSTEMS MAGAZINE
N −1
N −1
N −1
55
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