Aerospace and Electronic Systems Magazine April 2018 - 49

Miralles et al.

RADAR HARDWARE
This section introduces the main blocks of the radar hardware, including the antenna board, the receiver board, and the signal generation. The circuit-level block diagrams are shown in Figure 3.
The antenna board includes, in a single, planar printed circuit
board (PCB), 32 radiating elements: 16 for TX (in blue) and 16 for
RX (in red in Figure 3). They are placed in a rectangular configuration in such a manner that an unoccupied surface at the center of
the array arises. To achieve the desired operational bandwidth and
the desired range resolution, resonant slot patch antennas (RSPAs)
instead of traditional patch antennas are incorporated. A three-way
Wilkinson divider equally distributes the FMCW ramp, which is
generated by the DDS and PLL, to the two independent switch
chains and the receiver. The two switch chains are able to select the
proper antenna at the right time or to lead the signal to a terminated
port (50-Ω resistor) to accomplish orthogonality of the received
data streams under a TDM paradigm. A more detailed description
of the antenna board can be found in [16].
The receiver board consists of 16 direct-conversion receivers.
The RX signals are amplified by a low noise amplifier and then
fed to the mixers. A chirp distribution network splits up the chirp
signal and distributes it coherently to all 16 stages. Each stage has
its own amplifier to drive the LO input port of the mixer. The RX
signal is then mixed with the originally sent chirp and lowpass filtered. From the output of the receiver, the intermediate frequency
signals go directly to the digital board.
The main elements of the digital board are the Zynq, which is
a FPGA and an ARM processor in one chip; two 8-channel, 14-bit
ADCs, which run at 100 MHz; and an Ethernet interface.
For the radar system to be compact and multifunctional, a
lightweight, robust, and adaptable housing is needed. To fulfill
these requirements, a special housing was designed and 3D printed
in aluminum. In addition to the protection of the components, the
housing is used as a heat sink. All boards are thermally linked to
the housing and two cooling channels, which are connected to a
fan to enhance the heat dissipation of the system. Figure 4 shows a
photograph of the overall system with the 3D-printed housing. The
boxes show the TX and RX elements, the camera, and the two-axis
gimbal, which is mounted in the middle of the rectangular array.
The size of the housing is 23 × 25 × 16 cm. On the top of the housing, the opening of the cooling system can be seen.

WAVEFORM AND TIMING
This section describes the waveform and the timing of the MIMO
radar. The system uses linear chirps from 16 to 17 GHz. The upramp (tup = 100 μs) is followed by a down-ramp (20 μs), both of
which form a triangular chirp. The down-ramp is not considered
in the radar processing yet. Considering the up-ramp with a bandwidth B = 1 GHz and c0 as the speed of light, a range resolution of
ΔR =

c0
= 0.15 m
2B

(1)

is obtained. The range limit of the system can be calculated using
the sampling frequency of the ADC (fs = 100 MHz), which deterAPRIL 2018

Figure 4.

Picture of the 3D-printed housing with the antenna board and camera
mounted in the middle. The markers show where the TX and RX antennas and the camera are placed.

mines the maximum difference frequency because of the sampling
theorem:

Rmax

fs
2 = 750 m
=
B
2
tup
c0

(2)

The maximum range depends on the cross-section of the target and
the maximum emitted power but is limited by the maximum sampling frequency of the ADC. Taking that into consideration, in a
FMCW radar system, higher ranges produce higher frequencies.
The presented prototype is able to detect people at 150 m with 18
dBm of maximum output power.
Here, a MIMO cycle is composed of 16 up-ramps, where each
ramp is sent via a different TX antenna. To avoid interferences
among the TX signals and then achieve orthogonality, TDM is
used. With TDM, it is possible to assign the TX antenna to the RX
signal according to the timing scheme.
The timing of a MIMO cycle is shown in Figure 5. At the beginning, the system waits for a start command from the HMI. After
that, the first TX antenna is activated and sends the FMCW chirp.
The RX signals are captured by the ADC and stored in the FPGA.
After that, the data are transferred from the FPGA to the DDR
memory of the system via DMA. This procedure is repeated for
all 16 TX antennas and lasts, altogether, approximately 20 ms. The
radar beamforming algorithms are carried out in a matrix laboratory (MATLAB) environment. Therefore, the data of the complete
MIMO cycle are transferred via Ethernet to a workstation. After
the transfer, the radar processing is launched. With the current

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Table of Contents for the Digital Edition of Aerospace and Electronic Systems Magazine April 2018