Avionics News May 2020 - 49
Figure 2: A synchronous
R-S flip-flop symbol and
its truth table
required to trigger a level-activated flip-flop circuit. Any
input without the negation circle will be triggered by a
logic high, or 1.
Edge-triggered flip-flops will activate when the
triggering voltage is changing from low to high, or
from high to low. Edge-triggered flip-flops will use a
greater than symbol (>), known as a dynamic indicator
to denote the circuit is triggered on the edge. When a
negation symbol is used on an edge-triggered flip-flop,
it is indicating the circuit triggers when the voltage is
in transition from high to low, which is also known as
the negative edge, or downclock. If there is no negation
symbol, the circuit is triggered when the voltage is in
transition from low to high, which is also known as the
positive edge, or upclock.
Like the multivibrators described last month, the
outputs of these circuits are labeled Q and Q-NOT. The
Q output is used to define the state of the flip-flop circuit.
If Q is high, or equal to a logic 1, the flip-flop circuit is
set. If the Q output is a logic 0, or low, the flip-flop is in a
reset condition. Put another way, when a flip-flop is set, it
is storing a logic 1. When the flip-flop is reset, it is storing
a logic 0.
This brings us to our first flip-flop circuit, the R-S,
also known as an R-S latch. R-S stands for Set Reset. At
this time, I'm not quite sure why the engineers didn't call
that an S-R flip-flop, but that's a digression. Other than a
power supply and ground, the S-R flip-flop has two inputs
and two outputs. An S-R flip-flop can be asynchronous,
meaning the circuit is not controlled by any specific
timing pulse.
R-S flip-flops are level-activated. R-S flip-flops can
be synchronous or asynchronous. When an asynchronous
R-S flip-flop senses a logic 1 on the S input (set), Q
will be set, or a logic 1. The circuit will remain that way
(memory) until a logic 1 appears on the R input (reset),
at which time the Q output goes to a logic 0. If both
inputs are 0, no change will occur. If both inputs are 1,
something is wrong with the circuitry preceding the R-S
flip-flop. Simultaneous 1s are not allowed. Figure 1 shows
the symbol for an R-S flip-flop and its truth table.
A synchronous R-S flip-flop must satisfy its clock first.
In other words, the S or R inputs can change, but if the
clock level is low, no change will occur. If the clock level
is high, or a 1, a pulse on the S input will set the Q output,
and a pulse on the R input will reset the Q output to a
0. In other words, once the clock is taken care of, it will
Continued on following page
Figure 3: A D-type flip-flop
symbol and its truth table
avionics news
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may
2020
49
Avionics News May 2020
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