Aerospace and Electronic Systems Magazine August 2017 - 48

Acquisition of GNSS Signals with Secondary Code

Figure 1.

Basic diagram of the parallel code search implemented on an FPGA, using a buffer for faster processing.

The basic diagram of the parallel code search implemented on
a field-programmable gate array (FPGA) is shown in Figure 1. In
this figure, the incoming signal is stored in a memory at the sampling frequency for a faster processing during the acquisition. For
different frequencies of the local carrier replica, the circular correlation between the incoming code and the local code is computed
using FFTs. Then additional coherent or noncoherent integration
can be performed. This process is performed at the FPGA frequency, which is usually much higher than the sampling frequency, allowing a speeding up of the acquisition [24].
For the following, we will concentrate only on the processing
between the carrier removal and the extra coherent integration, i.e.
the circular correlation computed using FFTs.

DIRECT CORRELATION OVER THE SECONDARY CODE
PERIOD
The circular correlation can be performed over the entire tiered
code to synchronize with both primary and secondary codes simultaneously, as proposed in [11]. Using matrix notation, the circular
correlation can be written as
y = Cx = Xc,

(5)

where C is an N × N right circulant matrix with cT as first row, x is
the signal after the carrier removal, and X is an N × N left circulant
matrix with x as first column [25]. Since a circulant matrix can be
diagonalized by the discrete Fourier transform matrix F, we can
write
y = F −1 ((Fc)*  (Fx)),

(6)

where * denotes the conjugate operator and ○ denotes the Hadamard product (element by element product) [25]. Therefore, this
circular correlation can be implemented using FFTs as shown in
Figure 2, where the length of the FFTs is N. The corresponding
timing diagram is shown in Figure 14 (all the timing diagrams are
provided in appendix to not overload the core of the article), as48

Figure 2.

Implementation of the direct correlation over the secondary code period
(see (5) and (6)). See the timing diagram in Figure 14.

suming that several FFTs can be computed consecutively without
pause (this corresponds to the streaming implementation of some
FFTs [26]), and that the FFT has a latency of LN clock cycles (i.e.,
there are LN clock cycles between the last sample of the input sequence and the first sample of the first output sequence).
For an FPGA implementation, the FFT cores available require
an FFT length that is a power of two [26]-[29]. As mentioned
previously, the minimum value of N is 409,200 for the L5 signal,
thus the smallest power of two possible is 219 = 524,288. To have
this FFT length, the sampling frequency must be 26.2144 MHz
(524,288/(20 ms)). Otherwise, if another sampling frequency is
considered, zero-padding must be used, and the equivalent of two
code periods are needed (to keep the periodicity of the code and
avoid losses [30], [31]), and in this case the FFT length would be
1,048,576.
In any case, it is not possible to implement such FFT directly
since the required length is too large. Indeed, the maximum length
currently available with the Altera FFT core is 262,144 with the
variable streaming data flow (which consumes a tremendous
amount of resources) and 65,536 with the streaming and burst data
flows [26]; the maximum length is 65,536 with the Xilinx FFT
core [27]; 16,384 with the Lattice FFT core [28]; and 8,192 with
the Microsemi FFT core [29]. Nevertheless, the processing time
of the theoretical implementation of the direct correlation is given
in Table 1, without and with zero-padding. In the next section, we
will consider the computation of the circular correlation by combining the results of smaller circular correlations, which is more

IEEE A&E SYSTEMS MAGAZINE

AUGUST 2017



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