Aerospace and Electronic Systems Magazine August 2017 - 51

Leclère, Botteron, and Farine

IMPLEMENTATION OF THE POST-FFT SECONDARY CODE
REMOVAL WITH A MEMORY
Looking at (9), it can be seen that the correlation between the local
primary code p and each portion of the incoming code (x0, x1, ...)
needs to be performed only once. Only the combinations of the
different portions according to the secondary code delays differs.
However, this requires the storage of the correlation portions (r0,
r1, ...). The corresponding implementation using a memory to store
r0, r1, ..., and computing y0, y1, ... sequentially is shown in Figure 5.
The processing starts by accessing x0, x1, ..., computing their
correlation with the local code p, and storing the results into the
memory. Then, the memory is read and a combination is tested,
then the memory is read again and another combination is tested,
and so on and so forth. The process is then repeated for the next
data stream, as soon as it is possible to write again into the memory
without overwriting data not yet read. With this implementation,
the combinations are performed over vectors of NP instead of 2NP
for the pre-FFT implementations, which implies that the processing time is approximately halved compared to the pre-FFT sequential implementation.
With this implementation, the memory needed is twice NP NS ×
B1 bits to store the FFT outputs and twice NP (B1 + ⌈log2 NS⌉) bits
for the accumulation, where B1 denotes the number of bits used to
quantize the outputs of the inverse FFT (ri).

Figure 4.

Implementation of the pre-FFT secondary code removal (see (8)) computing each combination of the input in parallel. See the timing diagram
in Figure 16.

Figure 5.

Implementation of the post-FFT secondary code removal (see (9)) using
a memory to store correlation portions and computing each combination
of the output sequentially. See the timing diagram in Figure 18.

IMPLEMENTATION OF THE POST-FFT SECONDARY CODE
REMOVAL IN A SEQUENTIAL WAY
It is also possible to implement (9) without storing r0, r1, ..., but in
this case, they must be recomputed several times. The corresponding implementation computing y0, y1, ... sequentially is shown in
Figure 6.
The processing starts by accessing x0, x1, ..., computing their
correlation with the local code p, and combining the results according to the secondary code chips. The process is then repeated to test the next combinations. Then, the process is repeated
for the next data streams. With this implementation, since the
zero-padding is present at the input of the FFTs and for the combinations, the processing time is higher than with the pre-FFT
sequential implementation and with the post-FFT implementation with a memory.

Figure 6.

Implementation of the post-FFT secondary code removal (see (9))
computing each combination of the output sequentially. See the timing
diagram in Figure 19.

IMPLEMENTATION OF THE POST-FFT SECONDARY CODE
REMOVAL IN A PARALLEL WAY
As previously, it is also possible to compute each portion of the
output in parallel using NS accumulators, as shown in Figure 7.
The processing is similar to the previous post-FFT implementation, except that the FFTs are computed only once, since each accumulator accumulates when a new correlation portion is available, and that there are NS output available simultaneously (which
will require a slightly different detection process after that). Contrary to the pre-FFT parallel implementation, there is no need
to stop the stream between different data streams, therefore the
AUGUST 2017

Figure 7.

Implementation of the post-FFT secondary code removal (see (9))
computing each combination of the output in parallel. See the timing
diagram in Figure 20.

IEEE A&E SYSTEMS MAGAZINE

Table of Contents for the Digital Edition of Aerospace and Electronic Systems Magazine August 2017