Aerospace and Electronic Systems Magazine July 2017 Tutorial XI - 29

gation environments, where the signal may be affected by high
dynamics, shadowing, strong fadings, multipath effects, or ionospheric scintillation [11], [12]. On the basis of conventional PLL
architectures, some improvements have been proposed in the literature [13], [14], [15], but their performance have been overcome
by KF-based techniques [11], [12], [16], [17], [18]. The main drawback of KFs is the need of an exact knowledge of the system model
noise statistics' for an optimal behavior, thus being constrained by
the accuracy of the dynamic model and the a priori fixed system
parameters. In practice, those quantities may need to be somehow
adjusted to provide a robust solution [19], a problem that has been
solved by the so-called adaptive KFs (AKFs) [19]-[24].
Our previous experience on the use of KF synchronization schemes
for both communications [25], [26] and positioning systems [19], [27],
[28], [29], the lack of a unified analysis in the literature, and a clear
answer to the PLL versus KF dilemma ignited this work. From different
analysis carried out in the literature for specific scenarios, it seems clear
that KF schemes should, in general, be preferred in front of PLL-based
solutions, but the synchronization and aerospace communities seem still
reluctant to go further on theoretical analysis of such techniques and to
cross the gap between theory and implementation. Moreover, the advent of software-defined radio receivers in real-life applications [30],
[31] has confirmed the practical feasibility of this approach. The main
goal of this tutorial-style article is to provide a comprehensive overview
and unified framework. Therefore, this work is for the practitioner or
engineer who needs to solve real hands-on problems and the academic
or researcher willing to push forward on new advanced synchronization
techniques.
The notation used in this article is as follows: lowercase italics
for scalar variables, either deterministic or stochastic, both real or
complex; uppercase italics for constants; lowercase bold for vector variables, columnwise defined; uppercase bold for matrix variables; (·), (·)*, and (·)H stand for the transpose, conjugate, and
conjugate transpose (hermitic) operators, respectively; is an estimate of the true parameter value x at time k, given its value in time
k - 1;x ∼  ( μ x ,σ x2 ) is a random variable x Gaussian-distributed
with mean μx and variance σ x2; and ℜ(x) and I(x) stand for the real
and imaginary parts of x, respectively. More notation will be defined throughout the article, as needed.
JULY 2017, Part II of II

PLL-BASED ARCHITECTURES
CP synchronization techniques implemented during recent decades
in mass-market and industrial-grade positioning, communications,
and tracking systems receivers rely on well-established PLL-based
architectures [4], [32], [33]. First analyzed by Appleton in 1922
[34], early applications of PLLs were the control of receivers' local
oscillators, especially in FM demodulators and automatic volume
control circuits. In the early 1950s, they played an important role
in the development of color television [35], and the availability
of PLL integrated circuits in the mid-1960s facilitated their rapid
introduction into a wide range of consumer products, becoming
a key component of electronic devices for the next three decades
[36], [37], [38]. Nowadays, digital PLLs are widely used in modern communication systems [39] and are still the method of choice
in many applications, such as global navigation satellite systems
(GNSS) [3] and space communications [40], mainly because of
manufacturer's inertia on legacy solutions and well-proven technologies. Hereafter, the main PLL-based architectures and design
rules are summarized.

BASICS
In general, a PLL is built up with three main blocks: the discriminator or phase detector, the loop filter, and a numerically controlled
oscillator (NCO), which is nothing but an integrator. The main idea
is to obtain first an error signal (i.e., discriminator's output), which
is proportional to the CP error; then, this error goes through the loop

Figure 1.

Standard PLL architecture.

IEEE A&E SYSTEMS MAGAZINE

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